
PIC18F46J11 FAMILY
DS39932D-page 158
2011 Microchip Technology Inc.
REGISTER 10-12: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 (BANKED EEEh)
U-0
R/W-1
—
IC2R4
IC2R3
IC2R2
IC2R1
IC2R0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented:
Read as ‘0’
bit 4-0
IC2R<4:0>:
Assign Input Capture 2 (ECCP2) to the Corresponding RPn Pin bits
REGISTER 10-13: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (BANKED EF2h)
U-0
R/W-1
—
T1GR4
T1GR3
T1GR2
T1GR1
T1GR0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented:
Read as ‘0’
bit 4-0
T1GR<4:0>:
Timer1 Gate Input (T1G) to the Corresponding RPn Pin bits
REGISTER 10-14: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 (BANKED EF3h)
U-0
R/W-1
—
T3GR4
T3GR3
T3GR2
T3GR1
T3GR0
bit 7
bit 0
Legend:
R/W = Readable, Writable if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented:
Read as ‘0’
bit 4-0
T3GR<4:0>:
Timer3 Gate Input (T3G) to the Corresponding RPn Pin bits